RESEARCH:
Ing-Jer Huang’s research deal with computer engineering aspects of computer architecture, SoC platforms, design automation, system software, embedded systems, the Hardware-Software Co-design and Co-verification of SoC. His licensing technologies give related industries the ability to more quickly adjust to this shifting competitive landscape, such as Andes, ACard, ADMtek, ATChip, Faraday, GlobalUniChip, Himax, Holtek, Marvell, Microtime, RDC, Socle, ITRI, S&Q, Temento Systems, Via, etc. His licensing works can achieve the goals of coordination, focus and speed for the industries. He has been working on the development of SoC infrastructure and related IP’s to support real time on-chip tracing, debugging, verification and monitoring for advanced on-chip connection. In addition, he is leading a large-scale joint project and developing the hardware/software of a 3D graphics/stereo SoC for consumer electronics.

SELECTED PUBLICATIONS:
Hsu-Kang Dow, Ing-Jer Huang, Robert Rieger, Ko-Chi Kuo, Lan-Yuen Guo, Shih-Jung Pao: A Bio-Sensing System-on-Chip and Software for Smart Clothes. ICCE 2019

Ing-Jer Huang, Chun-Hung Lai, Yun-Chung Yang, Hsu-Kang Dow, Hung-Lun Chen: A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 663-670 (2018)

Tsun-Hsin Chang, Shao-Chieh Hou, Ing-Jer Huang A unified GDB-based source-transaction level SW/HW co-debugging. APCCAS 2016: 506-509

Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang Jain, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee: Full system verification of compatible microprocessors with a dual physical core verification platform. ISOCC 2016: 357-358

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT 2015: 1-4

LINKS:
https://dblp.uni-trier.de/pid/67/2758.html
https://www.youtube.com/watch?v=6Tx5sy1VaRg